vcr2n/4n/7n vishay siliconix document number: 70293 s-04027?rev. e, 04-jun-01 www.vishay.com 6-1 jfet voltage-controlled resistors
part number v gs(off) max (v) v (br)gss min (v) r ds(on) max ( ) vcr2n ?7 ?25 60 VCR4N ?7 ?25 600 vcr7n ?5 ?25 8000
continuous voltage-controlled resistance high off-isolation high input impedance gain ranging capability/wide range signal attenuation no circuit interaction simplified drive variable gain amplifiers voltage controlled oscillator agc the vcr2n/4n/7n jfet voltage controlled resistors have an ac drain-source resistance that is controlled by a dc bias voltage (v gs ) applied to their high impedance gate terminal. minimum r ds occurs when v gs = 0 v. as v gs approaches the pinch-off voltage, r ds rapidly increases. this series of junction fets is intended for applications where the drain-source voltage is a low-level ac signal with no dc component. key to device performance is the predictable r ds change versus v gs bias where: r ds bias r ds (@ v gs 0) 1? v gs v gs(off) these n-channel devices feature r ds(on) ranging from 20 to 8000 . all packages are hermetically sealed and may be processed per mil-s-19500 (see military information). d s g and case to-206aa (to-18) top view 1 23 s c to-206af (to-72) d g top view 1 23 4 vcr2n, VCR4N vcr7n for applications information see an105.
vcr2n/4n/7n vishay siliconix www.vishay.com 6-2 document number: 70293 s-04027 ? rev. e, 04-jun-01
gate-source, gate-drain voltage ? 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gate current 10 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation b 300 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature range ? 55 to 175 c . . . . . . . . . . . . . . . . . . . storage temperature ? 65 to 200 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature ( 1 / 16 ? from case for 10 sec.) 300 c . . . . . . . . . . . . . . . . . . . notes: a. t a = 25 c unless otherwise noted. b. derate 2 mw/ c above 25 c.
limits vcr2n VCR4N vcr7n parameter symbol test conditions typ a min max min max min max unit static gate-source breakdown voltage v (br)gss i g = ? 1 a, v ds = 0 v ? 55 ? 25 ? 25 ? 25 gate-source cutoff voltage v gs(off) v ds = 10 v, i d = 1 a ? 3.5 ? 7 ? 3.5 ? 7 ? 2.5 ? 5 v gate reverse current i gss v gs = ? 15 v, v ds = 0 v ? 5 ? 0.2 ? 0.1 na v gs = 0 v, i d = 10 ma 20 60 drain-source on-resistance r ds(on) v gs = 0 v, i d = 1 ma 200 600 ds(on) v gs = 0 v, i d = 0.1 ma 4000 8000 gate-source forward voltage v gs(f) v ds = 0 v, i g = 1 ma 0.7 v dynamic drain-source on-resistance r ds(on) v gs = 0 v, i d = 0 ma f = 1 khz 20 60 200 600 4000 8000 drain-gate capacitance c dg v gd = ? 10 v, i s = 0 ma f = 1 mhz 7.5 3 1.5 source-gate capacitance c sg v gs = ? 10 v, i d = 0 ma f = 1 khz 7.5 3 1.5 pf notes: ncb/npa/nt a. typical values are for design aid only, not guaranteed nor subject to production testing. 0 0.2 0.4 0.6 0.8 1 0 output characteristics (vcr2n) v ds ? drain-source voltage (v) ? 0.5 v ? 2.0 v ? 2.5 v ? 1.0 v ? 1.5 v 0 0.1 0.2 0.3 0.4 0.5 output characteristics (VCR4N) v ds ? drain-source voltage (v) ? 3.0 v 30 25 20 15 5 10 1.0 0 0.8 0.6 0.4 0.2 v gs(off) = ? 4 v v gs = 0 v v gs(off ) = ? 4.2 v v gs = 0 v ? 4.0 v ? 3.5 v ? 1.5 v ? 2.0 v ? 3.0 v ? 2.5 v i d ? drain current (ma) i d ? drain current (ma)
vcr2n/4n/7n vishay siliconix document number: 70293 s-04027 ? rev. e, 04-jun-01 www.vishay.com 6-3 0 0.2 0.4 0.6 0.8 1 output characteristics (vcr7n) v ds ? drain-source voltage (v) 200 0 160 120 80 40 ? 0.5 v ? 2.0 v ? 1.0 v ? 1.5 v v gs(off) = ? 2.5 v v gs = 0 v i d ? drain current (ma) a simple application of a fet vcr is shown in figure 1, the circuit for a voltage divider attenuator. v in figure 1. simple attenuator circuit v out r ? + v gs vcr the output voltage is: r + r ds v in r ds v out = it is assumed that the output voltage is not so large as to push the vcr out of the linear resistance region, and that the r ds is not shunted by the load. the lowest value which v out can assume is: r + r ds(on) v in r ds(on) v out(min) = since r ds can be extremely large, the highest value is: v out(max) = v in
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